1. Field of the Invention
The present invention relates to a semiconductor device, a manufacturing method thereof, and a data processing system, and more particularly relates to a semiconductor device having a vertical transistor, a manufacturing method thereof, and a data processing system.
2. Description of Related Art
In semiconductors, particularly in memory devices, chip sizes are reduced year by year from a viewpoint of cost reduction. In response to this trend, employment of a vertical transistor having a 4F2 configuration has been progressed for cell transistor in DRAM (Dynamic Random Access Memory). As for transistors of peripheral circuits, because demand for downscaling is not so high as that of cell transistors, conventional planar transistors are still employed. However, when configurations of cell transistors and configurations of transistors for peripheral circuits are different, the number of processes greatly increases. Accordingly, employment of a vertical transistor having a 4F2 configuration has been studied recently for transistors of peripheral circuits.
In a vertical transistor incorporated in a peripheral circuit, two silicon pillars close to each other are used as described in Japanese Patent Application Laid-open No. 2008-288391. One of the two silicon pillars is used for a channel, an impurity diffusion layer is provided in each of an upper part and a lower part of this silicon pillar, and a side surface thereof is covered with a gate electrode via a gate dielectric film. The other silicon pillar is a dummy silicon pillar to extend the length of the gate electrode to a lateral direction, and a gate contact plug is provided by using an extended portion.
Formation of an impurity diffusion layer at an upper part (hereinafter, “upper diffusion layer”) and a gate contact plug is briefly explained. First, a silicon pillar and a gate electrode are formed, and thereafter an interlayer dielectric film is deposited on the entire surface of a substrate while leaving a hardmask for formation of silicon pillars. The surface is planarized by CMP (Chemical Mechanical Polishing). Subsequently, an opening of the interlayer dielectric film is formed by a lithography method at a position above a silicon pillar for a channel, and only a hardmask positioned at an upper part of the silicon pillar for the channel is exposed. The exposed hardmask is removed by thermal phosphoric acid, and the upper diffusion layer is formed within the opening. Thereafter, an interlayer dielectric film is deposited, a contact hole is provided at a position near a boundary between a dummy silicon pillar and the gate electrode, and a conductor is embedded into the contact hole, thereby forming a gate contact plug. Insulation between the gate contact plug and the dummy silicon pillar is secured by a hardmask remaining at an upper part of the dummy silicon pillar.
When the chip size becomes smaller, the distance between two silicon pillars constituting one vertical transistor also needs to be narrower. In this case, positioning at the time of forming an opening in the interlayer dielectric film by using the lithography method becomes difficult. Consequently, the hardmask positioned at the upper part of the dummy silicon pillar is also removed, and there can be a case that the dummy silicon pillar and the gate contact plug are short-circuited.